Sniffing out Teensy 4.0 for UltraRedundancy

Purpose

To get an idea of how we'd design a PCB for this architecture.

Teensy 4.0 Features

• The FlexIO is capable of supporting a wide range of protocols including, but not limited to: UART, I2C, SPI, I2S, camera interface, display interface, PWM waveform generation, etc. The module can remain functional when the chip is in a low power mode provided the clock it is using remain active. There's two of these which suits our design. (FlexIO1 FlexIO2)
• General Purpose I/O Modules: Used for general purpose input/output to external ICs. Each GPIO module supports up to 32 bits of I/O. (GPIO1 GPIO2 GPIO3 GPIO4 GPIO5) Is this enough for our purpose?
• RTWDOG: Watch Dog, The RTWDG module is a high reliability independent timer that is available for system to use. It provides a safety feature to ensure software is executing as planned and the CPU is not stuck in an infinite loop or executing unintended code. If the WDOG module is not serviced (refreshed) within a certain period, it resets the MCU. Windowed refresh mode is supported as well.
• Vin is 3.6 to 5.5 volts

Teensy 4.0 Pinout